1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and, more particularly, to a delay locked loop having improved high frequency characteristics and yield.
2. Description of the Related Art
As microprocessors approach operating speeds of greater than 1 GHz, system bus clocks and memory devices for improving the performance of computer systems also need to operate at high speeds. Super high-speed products such as synchronous DRAMs (hereinafter, referred to as “SDRAMs”) or RAMBUS DRAMs (hereinafter, referred to as “RDRAMs”) have been used as memory devices.
SRAMs and RDRAMs are synchronized with clock signals and input data into memory cells or output data from memory cells during valid data windows. The clock signals are input into a pin of a device and distributed throughout the entire device. Thus, clock signals reaching a device relatively far from an input pin are much more delayed than clock signals reaching a device right adjacent to the input pin.
It is difficult to maintain the synchronization between devices in SDRAMs or RDRAMs due to this delay. A delay locked loop (hereinafter, referred to as “DLL”) is used to maintain this synchronization. The DLL generates internal clock signals which are in synchronization with an external clock.
More particularly, the internal circuit blocks are synchronized with edges of the internal clock signals and output data are located at the center of valid data windows.
FIG. 1 shows the structure of a conventional DLL 100. The DLL 100 generates first internal clock signal TCLK and second internal clock signal TCLK 90 in response to and in synchronization with an external clock signal EXT_CLK. The DLL 100 includes a first amplifier 101, a first duty corrector 102, a basic clock generator 103, a mixer 104, a 90° phase shift block 105, a second amplifier 106, a third amplifier 107, a clock buffer 108, a buffer 109, a second duty corrector 110, an output replica 111, a phase detector 112, and a digital-to-analog converter 113.
The first amplifier 101 generates a first clock signal SS_CLK having a small voltage swing range in response to the external clock signal EXT_CLK. In general, the external clock signal EXT_CLK is input at a transistor-transistor-logic (TTL) level and thus its voltage swing range is about 0˜VDD.
The first amplifier 101 generates the first clock signal SS-CLK having a small voltage swing range of about 400 mV˜800 mV. Thus, power consumption of the RDRAM decreases. The first clock signal SS_CLK may be distorted to 50% duty by the first amplifier 101. Thus, the distorted duty is compensated for via the first duty corrector 102 and then is fed back to the first amplifier 101. Also, the first clock signal SS_CLK includes a pair of signals having complementary levels.
The basic clock generator 103 generates eight basic clock signals REF_CLK, which are each shifted 45 degrees, in response to the first clock signal SS_CLK having a small voltage swing range. The mixer 104 generates a second clock signal M_CLK by mixing two of the basic clock signals REF_CLK selected in response to the output of the digital-to analog converter 113.
The 90° phase shift block 105 generates a third clock signal CLK0 and a fourth clock signal CLK90, which are each 90 degrees out-of-phase with each other, in response to the second clock signal M_CLK. The third clock signal CLK0 has substantially the same phase as the second clock signal M_CLK. The fourth clock signal CLK90 is 90 degrees out-of-phase with the third clock signal CLK0. The 90° phase shift block 105 has a structure where a plurality of delay devices 105a, 105b, 105c, and 105d are connected in series to one another and is an open loop type.
The second amplifier 106 and the third amplifier 107 respectively output the third clock signal CLK0 and the fourth clock signal CLK90 having a CMOS voltage swing range (i.e., 0˜VDD) in response to the third signal CLK0 and the fourth signal TCLK90 having a small voltage swing range (i.e., 400 mV˜800 mV). The third clock signal CLK0 and the fourth clock signal CLK90, which have been amplified to have a CMOS voltage swing range, are supplied to the clock buffer 108.
The clock buffer 108 includes drivers 108a and 108b for driving loads. The third clock signal CLK0 is buffered by the clock buffer 108 and the buffer 109 and output as the first internal clock signal TCLK. The fourth clock signal CLK90 is buffered by the clock buffer 108 and output as the second internal clock signal TCLK90. The first and second internal clock signals TCLK and TCLK90 are CMOS levels with 90° phase differences.
The second internal clock signal TCLK90 is input to the second duty corrector 110, corrected so that the first and second internal clock signals TCLK and TCLK90 have 50% duty, and fed back to the second amplifier 106 and the third amplifier 107. Also, the second internal clock signal TCLK90 is input to the output replica 111 which reflects loads of the path of the first internal clock signal TCLK. Thus, the output signal of the output replica 111 is substantially equal to the first internal clock signal TCLK.
The phase detector 112 detects the phase difference between the output of the output replica 111 and an external clock signal EXT_CLK. Then, the phase detector 112 compares the phase difference between the edges of the second internal clock signal TCLK 90 and the external clock signal EXT_CLK.
The operation result of the phase detector 112 is input to the digital-to-analog converter 113 and used to generate coding data. The coding data, which is output from the digital-to-analog converter 113, is provided to the mixer 104 and used to mix the basic clock signals REF_CLK selectively. Thus, the phases of the second clock signal M_CLK and the third clock signal CLK0 are in synchronization with the phase of the external clock signal EXT_CLK. Finally, the phase of the first internal clock signal TCLK is also in synchronization with the phase of the external clock signal EXT_CLK.
Although the first internal clock signal TCLK is in synchronization with the external clock signal EXT_CLK, it has duty errors. In other words, it is generally preferable for clock signals to have 50% duty. However, the first internal clock signal TCLK generated by the conventional DLL 100 does not have 50% duty.
Such duty errors are caused by skew between the third and fourth clock signals CLK0 and CLK90 in the 90° shift block 105, the difference in DC offsets between the second and third amplifiers 106 and 107, gain difference during the generation of the first and second internal clock signals TCLK and TCLK90, fan-out difference, and parasitic load difference.
In particular, the 90° phase shift block 105 has an open loop structure and thus it increases the amount of skew between the third and fourth clock signals CLK0 and CLK90 based on changes in temperature and supply voltage.
The second duty corrector 110 is used to correct the duty errors in the first internal clock signal TCLK. However, the second duty corrector 110 is inappropriate for correcting duty errors in both the first and second internal clock signals TCLK and TCLK90. For example, assuming that the first internal clock signal TCLK has 48% duty and the second internal clock signal TCLK90 has 52% duty, the second duty corrector 110 reduces the duty of the second internal clock signal TCLK90 by about 2% to bring it to 50% duty. As a result, the duty of the first internal clock signal TCLK is lowered from 48% to 46% and thus the duty errors in the first internal clock signal TCLK is increased. Consequently, the second duty corrector 110 is essentially inappropriate for correcting duty errors in the first and second internal clock signals TCLK and TCLK90.
The duty error in the first internal clock signal TCLK causes shortage of margin of the output time of data terminal DQ (tQ: external clock to DQ output time) centered at the edge of the first internal clock signal TCLK. As a result, the yield of RDRAMs is decreased. Consequently, a DLL is required to maintain 50% duty and synchronize the phase of the first internal clock signal TCLK with the phase of the external clock signal EXT_CLK.